1. Field of the Invention
The present invention relates to a transistor array and, more particularly, to a self-protecting transistor array.
2. Description of the Related Art
An open drain output circuit is an output circuit that pulls the voltage on an output pad to ground when turned on, and isolates the output pad from ground when turned off. The open drain output circuit typically utilizes an NMOS transistor to control the voltage on the output pad during normal operation, and an electrostatic discharge (ESD) clamp, such as a grounded-gate NMOS transistor, to control the voltage on the output pad during an ESD event.
FIG. 1 shows a circuit diagram that illustrates a prior-art open drain output circuit 100. As shown in FIG. 1, circuit 100 includes an output driver 110, an NMOS transistor M1, and a grounded-gate NMOS transistor M2. NMOS transistor M1 has a drain connected to an output pad 112, a gate connected to the output of driver 110, and a source connected to ground. NMOS transistor M2 has a drain connected to output pad 112. In addition, NMOS transistor M2 has a gate, a body, and a source connected to ground.
During normal operation, output driver 110 of circuit 100 controls the on and off state of NMOS transistor M1. When turned on, NMOS transistor M1 pulls the voltage on output pad 112 down to ground. When turned off, NMOS transistor M1 electrically isolates output pad 112 from ground.
During an ESD event, transistor M2 functions as an ESD clamp by limiting the maximum voltage on output pad 112. When the voltage on output pad 112 rises sharply with respect to ground, the junction of the n+ drain and the p− body of transistor M2 becomes reverse biased, and then breaks down. When the junction breaks down, a hole current flows from the junction through the p− body to the p+ body contact, past the n+ source region.
The hole flow locally increases the potential which, in turn, forward biases the body-to-source junction, thereby turning on a parasitic npn bipolar transistor and substantially increasing the current flow. The n+ drain of transistor M2 forms the n+ collector of the parasitic npn bipolar transistor, while the p− body forms the p− base and the n+ source forms the n+ emitter. Thus, transistor M2 turns on at a triggering point, and then snaps back to provide a low resistance current path when the body-to-source junction becomes forward biased.
It is common practice to form NMOS transistor M1 as a transistor array. FIGS. 2A and 2B show plan views that illustrates examples of two prior-art, NMOS transistor arrays 200 and 202, respectively. As shown in FIG. 2, arrays 200 and 202 both include a number of spaced-apart n+ source strips S, and a number of spaced-apart n+ drain strips D such that one drain strip D lies between each adjacent pair of source strips S.
Further, arrays 200 and 202 include a number of polysilicon gate strips P such that a gate strip P lies over and between each adjacent source strip S and drain strip D. Arrays 200 and 202 additionally include a p+ body contact region B, and a number of contacts C that are connected to the source strips S, the drain strips D, and the body contact region B.
In the present example, all of the contacts C connected to all of the drain strips D are electrically connected to output pad 112. Arrays 200 and 202 differ only in the arrangement of the p+ body contact region B, and illustrate that the p+ body contact regions B can have a number of different shapes.
One problem with using a transistor array, such as array 200, is that it is difficult to protect the transistor array from ESD damage. Although grounded-gate NMOS transistor M2 provides ESD protection, a number of different factors, such as current crowding and the different gate potentials of transistors M1 and M2, can cause localized areas of transistor array 200 to be permanently damaged by an ESD event before transistor M2 can turn on and protect transistor array 200. Thus, there is a need for an ESD clamp which can provide ESD protection for an open drain output circuit.